AMD Unveils Spartan UltraScale+ FPGAs for Cost-Sensitive Edge Applications

AMD Unveils Spartan UltraScale+ FPGAs for Cost-Sensitive Edge Applications

AMD has announced the launch of its Spartan UltraScale+ FPGA family, the latest addition to its extensive portfolio of cost-optimized FPGAs and adaptive SoCs. Built on proven 16nm technology, the Spartan UltraScale+ devices are designed to cater to the growing demand for high-performance, power-efficient, and secure solutions in cost-sensitive edge applications.

According to Kirk Saban, corporate vice president of AMD's Adaptive and Embedded Computing Group, "For over 25 years the Spartan FPGA family has helped power some of humanity's finest achievements, from lifesaving automated defibrillators to the CERN particle accelerator advancing the boundaries of human knowledge." He added that the enhanced security features, common design tools, and long product lifecycles of the Spartan UltraScale+ family "further strengthen our market-leading FPGA portfolio and underscore our commitment to delivering cost-optimized products for customers."

One of the key highlights of the Spartan UltraScale+ FPGAs is their high I/O counts and flexible interfaces, enabling seamless integration and efficient interfacing with multiple devices or systems. The family boasts the industry's highest I/O to logic cell ratio among FPGAs built on 28nm and below process technology, with up to 572 I/Os and voltage support up to 3.3V. This makes them well-suited for edge sensing and control applications that require any-to-any connectivity.

The Spartan UltraScale+ family is also designed with power efficiency in mind. AMD estimates that these FPGAs offer up to a 30 percent reduction in power compared to the 28nm Artix 7 family, thanks to the 16nm FinFET technology and hardened connectivity. Additionally, they are the first AMD UltraScale+ FPGAs to feature a hardened LPDDR5 memory controller and PCIe Gen4 x8 support, providing both power efficiency and future-ready capabilities.

Security is another area where the Spartan UltraScale+ FPGAs shine. They offer the most state-of-the-art security features in AMD's cost-optimized FPGA portfolio, including support for post-quantum cryptography with NIST-approved algorithms for IP protection, PPK/SPK key support for managing obsolete or compromised security keys, and a permanent tamper penalty to protect against misuse. The enhanced single-event upset performance also helps ensure fast and secure configuration with increased reliability.

To support the development of hardware and software for the Spartan UltraScale+ FPGAs, AMD provides the Vivado Design Suite and Vitis Unified Software Platform. These tools allow designers to leverage the productivity benefits and included IPs via a single designer cockpit from design to verification.

AMD expects sampling and evaluation kits for the Spartan UltraScale+ FPGA family to be available in the first half of 2025, with documentation available today and tools support starting with the AMD Vivado Design Suite in the fourth quarter of 2024.

As the demand for high-performance computing at the edge continues to grow, AMD's latest offering is well-positioned to meet the needs of customers in various industries, including embedded vision, healthcare, industrial networking, robotics, and video applications.

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